IMPLEMENTATION OF INTERRUPTS


STATUS REGISTER (SR, aka SW)

   #  ... 7 6 5 4 3 2 1 0
      ... 0 1 1 0 1 0 1 0


   .
   .
   .

 # 7    - mode [0=monitor/1=user]

 # 6..4 - high..low priority interrupts [0=disabled/1=enabled]

 # 3    - addressing mode [0=absolute/1=relative]

 # 2..1 - caches [0=disabled/1=enabled]

 # 0    - pipeline [0=disabled/1=enabled]


PROGRAM COUNTER (PC, aka IC)

   Absolute/relative address of the next instruction

BASE REGISTER (BR)

   Point of reference for PC in relative addressing mode

STACK POINTER (SP)

   Addres of activation record of the most recent interrupt

           .
           .
2068:      .
2070:    LOAD  R7 @4000            BR = 2048
2072:    ADD   R7 #100       <---- PC =   24
2074:    STORE R7 @4000            SR = ... 11111000
2076:      .                       SP = nil
           .
           .

var INTERRUPT_VECTOR: array [0..M] of ^program;

{
00:  ADDR_0 {SRVC for interrupts class 0}
01:  ADDR_1 {SRVC for interrupts class 1}
02:  ADDR_2 {SRVC for interrupts class 2}
 .
 .
 .
M :  ADDR_M {SRVC for interrupts class M}
}

INTERRUPT CLASS N

type ACTIVATION_RECORD = BEGIN
                             context_saved: ^data;
                             PC_saved:      ^program;
                             SR_saved:       status_word;
                             SP_saved:      ^data
                         END

var temp: ^ACTIVATION_RECORD;

BEGIN {H/W implemented uninterruptable sequence}
    NEW(temp);
    temp.PC_saved := PC; {24}
    temp.SR_saved := SR; {... 11111000}
    temp.SP_saved := SP; {nil}
    SP := temp; {280}
    SR := ... 00000000;
{mode=monitor, interrupts=disabled,addressing=absolute}
    PC := INTERRUPT_VECTOR[N] {120}
END {H/W implemented uninterruptable sequence}

{Context save}

120: new(SP.context_saved);
122: SP.context_saved := R0..R15,BR,...;  
124: SR := SR + 64 
{hi priority interupts enabled}    BR = 2048
126: ...                     <---- PC = 126
                                   SR = ... 01000000
                                   SP = 280

STACK OF ACTIVE (UNFINISHED) INTERRUPTS

SP ---> context_saved ---> R0..R15,BR,...
        PC_saved
        SR_saved
        SP_saved ---> context_saved ---> R0..R15,BR,...
                      PC_saved
                      SR_saved
                      SP_saved ---> context_saved ---> R0..R15,BR,...
                                    PC_saved
                                    SR_saved
                                    SP_saved ---> ... 
                                                    .
                                                    .  nil

RETURN (RTN):

BEGIN {H/W implemented uninterruptable sequence}
    PC := SP.PC_saved {24}
    SR := SP.SR_saved {... 11111000}
    temp := SP;
    SP := SP.SP_saved; {nil}
    dispose(temp)
END {H/W implemented uninterruptable sequence}